Ray tracing on the cell processor back
(L) [2006/03/15] [Phantom] [Ray tracing on the cell processor] Wayback!While looking for ray tracing & cell related info I stumbled upon this paper:
[LINK http://www.research.ibm.com/people/a/ashwini/E3%202005%20Cell%20Blade%20reports/TRE%20demo%20-%20final.pdf]
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Whatever
(L) [2006/03/15] [Ho Ho] [Ray tracing on the cell processor] Wayback!On somewhat related note:
[LINK http://ps3.ign.com/articles/696/696056p1.html]
Ken Kutaragi confirmed that the PlayStation 3 will require the hard drive peripheral and the unit will ship with the system right out of the box.
In total, it will be 60GB big, be completely upgradeable, and support Linux OS. Additionally, the peripheral will act as a home server and allow users to store various forms of media to be pulled up elsewhere.
So, anyone going to buy PS3 or two just for a home cluster?
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In theory, there is no difference between theory and practice. But, in practice, there is.
Jan L.A. van de Snepscheut
(L) [2006/03/15] [lycium] [Ray tracing on the cell processor] Wayback!AAAAAAARGH RETARDED FORUM!!!
[oh and thanks for the link phantom, checking it now :)]
(L) [2006/03/16] [tbp] [Ray tracing on the cell processor] Wayback![LINK http://www.reghardware.co.uk/2006/03/15/amd_clearspeed_opteron_maths_co-pro/]
I'm much more interested by something like that, maybe due to 68881 nostalgia, than those way over hyped Cell (you'll notice that it's a paper from IBM about ray casting, not tracing).
There's not much more information on ClearSpeed's web, but Intel is also apparently interested.
Lycium, how can someone be so wrong in only one post?
Intel has nothing to show and won't for quite some time. Their next chips will only be the same crap they're serving atm, with a few knobs tweaked. No mem controller, no proper multicore. Move along, nothing to see here.
Then i don't know what you're doing wrt login, i've made sure to canonicalize the server name and tried to log in from IE, firefox and half a dozen other browsers without any trouble (on doze & linux). So i suspect it's a typical EBCAK.
(L) [2006/03/16] [Ho Ho] [Ray tracing on the cell processor] Wayback![LINK http://www.realworldtech.com/includes/templates/articles.cfm?ArticleID=RWT030906143144&mode=print]
I wouldn't call Conroe "the same old". It is a huge step forward from Netburst for Intel. AMD will have nothing to put against the 3.33GHz EE for quite some time. The shared 4MiB L2 seems quite nice for ray-tracing. It should certainly be better than 2x1/2MiB we have now.
Though first of those CPU's will be availiable around Q3 this year and EE Q4 or Q1-07.
_________________
In theory, there is no difference between theory and practice. But, in practice, there is.
Jan L.A. van de Snepscheut
(L) [2006/03/18] [tbp] [Ray tracing on the cell processor] Wayback!That's the same IDF PR link Ho Ho already posted, but in a paragraph-per-page format [SMILEY Wink]
(L) [2006/03/18] [lycium] [Ray tracing on the cell processor] Wayback!damn, should have read his post more thoroughly :/
</lamer>
(L) [2006/05/03] [tbp] [Ray tracing on the cell processor] Wayback!Educated comparison for a change,
[LINK http://www.anandtech.com/printarticle.aspx?i=2748]
(L) [2006/05/03] [Ho Ho] [Ray tracing on the cell processor] Wayback!I was just about to post it here [SMILEY Smile]
Two especially interesting bits:
(L) [2006/05/17] [tbp] [Ray tracing on the cell processor] Wayback!Hmm.
[LINK http://www.theinquirer.net/?article=31761]
(L) [2006/05/17] [Ho Ho] [Ray tracing on the cell processor] Wayback!Some interesting info about the K8L (translated from one other forum):
CPU IO has been redesigned for 4 cores, original Opteron has been designed for 2 from the beginning.
L2 is not shared between CPUs but there is added shared L3.
Physical address space has been increased from 40bit to 48bits. That means now it can use up to 256TiB of RAM instead of 1TiB. Should be enough for a while [SMILEY Smile]
Has integrated DDR2 memory controller. DDR3 and FBDIMM will be used in later iterations, FBDIMM should be availiable in 2008H1
64bit FP units have been replaced with 128bit ones. In one cycle it can execute two 128bit vector instructions and two load instructions. Basically the same as Conroe.
Instruction prefetching is more agressive. They are now read in 32B instead of 16B.
Some new instructions for bit manipulation and data moving.
Per cycle performance should be comparable with Conroe. Intel can extract more parallelism with it's four decoders and bigger execution ports but K8L has lower memory latency. Who wins depends on MHz. Yay for yet another MHz race [SMILEY Smile]
One interesting thing is the support for specialized co-processors. Basically you can put any kind of processor in one of the CPU slots on the motherboard. May it be either java/.Net, cryptography or anything else, perhaps even something for ray tracing [SMILEY Smile]
Sources:
[LINK http://www.realworldtech.com/forums/index.cfm?action=detail&id=67239&threadid=67239&roomid=11]
[LINK http://www.theregister.co.uk/2006/05/16/amd_next_gen/]
[LINK http://news.com.com/AMD+unveils+architecture+for+its+next+generation+of+chips/2100-1006_3-6072742.html?tag=nefd.lede[/quote]]
_________________
In theory, there is no difference between theory and practice. But, in practice, there is.
Jan L.A. van de Snepscheut
(L) [2006/05/17] [tbp] [Ray tracing on the cell processor] Wayback!"HyperTransport 3.0, recently approved by the standards body that governs the development of the technology, will accomplish 5.2 gigatransfers (5.2 billion transfers of data) per second, Moore said"
Gigatranfers? What does it give in standard library of congress per second?
Geez.
Out of order L/S. Finally. It's a bit thin on details but...
(L) [2006/05/17] [Ho Ho] [Ray tracing on the cell processor] Wayback!I think gigatransfers is the number of packets sent. Too bad I don't know the size of one packet [SMILEY Smile]
_________________
In theory, there is no difference between theory and practice. But, in practice, there is.
Jan L.A. van de Snepscheut
(L) [2006/05/17] [tbp] [Ray tracing on the cell processor] Wayback!16 bits (well it's adjustable but there's 16 bits worth of payload max). Now 5.2G/s is the advertised transfer rate, thusly 1 transfer = 1 bit = ??? library of congress.
(L) [2006/05/17] [Ho Ho] [Ray tracing on the cell processor] Wayback![LINK http://www.hypertransport.org/tech/tech_faqs.cfm#13]
7. At what clock speeds does HyperTransport technology operate?
HyperTransport technology devices are designed to operate at multiple clock speeds from 200MHz up to 2.6 GHz, and utilize double data rate (DDR) technology transferring two bits of data per clock cycle, for an effective transfer rate of up to 5.2 Gigatransfers/sec in each direction. Since transfers can occur in both directions simultaneously, aggregate transfer rates of 20.8 Gigabytes/second and 41.6 Gigabytes/second can be achieved with 16-bit wide and 32-bit wide link configurations respectively. To allow for system design optimization, the clock speed of the receive and transmit links may be set at different rates.
_________________
In theory, there is no difference between theory and practice. But, in practice, there is.
Jan L.A. van de Snepscheut
(L) [2006/05/17] [tbp] [Ray tracing on the cell processor] Wayback!KK, i had the peak rate mixed up. I'll put the blame on that gigatransfer non-sense, so please stop it at once, there's enough marketing stunts as is.
PS: show me a system with 32bit wide (external) HT links, eh.
(L) [2006/05/17] [Ho Ho] [Ray tracing on the cell processor] Wayback!I think 32bit HT links might be used in some cluster configurations where you stitch together several boards into one.
It should be possible to connect about eight boards directly with HT links (think of a 3d box with boards at the corners). With each one of those having 8x quadcore CPU's it makes one hell of a computing monster. Having 256 cores directly connected should be enough for instant GI at interactive framerates [SMILEY Smile]
Though I have heard AMD speaking of 32 CPU boards. It might be that they meant several layers of boards connected with HT.
_________________
In theory, there is no difference between theory and practice. But, in practice, there is.
Jan L.A. van de Snepscheut
(L) [2006/05/17] [tbp] [Ray tracing on the cell processor] Wayback!So says the marketing department.
Now a real, shipping, system: [LINK http://www.cray.com/products/xd1/]
Damn, they don't provide gigatransfer figures.
EDIT: perhaps that wasn't clear, but i mean yes that's 32bit HT, but a) on a freaking cray b) they go by grapes of 12, not 32 or 256.. (topology, latency etc).
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